Field of the Disclosure
The present disclosure relates generally to an apparatus for and a method of a supply modulator (SM) for a power amplifier (PA), and more particularly, to an apparatus for and a method of an SM for a PA that supports an average power tracking (APT) mode with a high voltage and to an SM for a PA that is efficient and has optimal performance in an envelope tracking (ET) mode.
Description of the Related Art
A switched mode power supply (SMPS) provides a regulated direct current (DC) supply that can deliver more power for a given size, cost, and weight of a power unit.
FIG. 1A is a schematic diagram of a buck converter 100 used in an SMPS circuit where a DC output voltage Vout must be lower than a DC input voltage Vin.
Referring to FIG. 1A, the buck converter 100 includes a third p-channel metal oxide semiconductor (PMOS) transistor P3, a third n-channel MOS (NMOS) transistor N3, an inductor 101, a capacitor 103, and a load, depicted as a resistor 105.
The third PMOS transistor P3 includes a source for receiving Vin, a gate to turn the third PMOS transistor P3 on and off, and a drain connected to one end of the inductor 101 and a drain of the third NMOS transistor N3. The third NMOS transistor N3 includes a gate for turning the third NMOS transistor N3 on and off and a source connected to a ground potential. The third PMOS transistor P3 and the third NMOS transistor N3 are turned on/off and off/on, respectively.
The inductor 101 includes a second end connected to a first end of the capacitor 103 and a first end of the load resistor 105 at which Vout is generated, where second ends of the capacitor 103 and the load resistor 105 are connected to the ground potential.
FIG. 1B is a graph of Vout versus Vin for the buck converter 100, which illustrates that Vout is less than Vin.
FIG. 2A is a schematic diagram of a boost converter 200 used in an SMPS circuit where a DC output voltage Vout must be higher than a DC input voltage Vin.
Referring to FIG. 2A, the boost converter 200 includes an inductor 201, a first PMOS transistor P1, a first NMOS transistor N1, a capacitor 203, and a load, depicted as a resistor 205.
The inductor 201 includes a first end for receiving Vin and a second end connected to a drain of the first PMOS transistor P1 and a drain of the first NMOS transistor N1.
The first PMOS transistor P1 includes a source connected to a first end of the capacitor 203 and a first end of the load resistor 205 at which Vout is generated, and a gate to turn the first PMOS transistor P1 on and off. Second ends of the capacitor 203 and the load resistor 205 are connected to a ground potential. The first NMOS transistor N1 includes a gate for turning the first NMOS transistor N1 on and off and a source connected to the ground potential. The first PMOS transistor P1 and the first NMOS transistor N1 are turned on/off and off/on, respectively.
FIG. 2B is a graph of Vout versus Vin for the boost converter 200, which illustrates that Vout is greater than Vin.
FIG. 3A is a buck-boost converter 300 used in an SMPS circuit where a DC output voltage Vout must be either less that or higher than a DC input voltage Vin. The buck-boost converter 200 may operate as either a buck converter in buck mode or a boost converter in boost mode.
Referring to FIG. 3A, the buck boost converter 300 includes a first PMOS transistor P1, a first NMOS transistor N1, an inductor 301, a third PMOS transistor P3, a third NMOS transistor N3, a capacitor 303, and a load, depicted as a resistor 305.
The third PMOS transistor P3 includes a source for receiving Vin, a gate to turn the third PMOS transistor P3 on and off, and a drain connected to a first end of the inductor 301 and a drain of the third NMOS transistor N3. The third NMOS transistor N3 includes a gate for turning the third NMOS transistor N3 on and off and a source connected to a ground potential. In buck mode, the third PMOS transistor P3 and the third NMOS transistor N3 are turned on/off and off/on, respectively, where the first PMOS transistor P1 and the first NMOS transistor N1 are off.
The inductor 301 includes a second end connected to a drain of the first PMOS transistor P1 and a drain of the first NMOS transistor N1.
The first PMOS transistor P1 includes a source connected to a first end of the capacitor 303 and a first end of the load resistor 305 at which Vout appears, and a gate to turn the first PMOS transistor P1 on and off. Second ends of the capacitor 303 and the load resistor 305 are connected to the ground potential. The first NMOS transistor N1 includes a gate for turning the first NMOS transistor N1 on and off and a source connected to the ground potential. In boost mode, the first PMOS transistor P1 and the first NMOS transistor N1 are turned on/off and off/on, respectively, where the third PMOS transistor P3 and the third NMOS transistor N3 are off.
FIG. 3B is a graph of Vout versus Vin for the boost converter 300 for both buck mode and boost mode, which illustrates that Vout can be less than, equal to, or greater than Vin.
The efficiency of each of the buck, boost, and buck-boost converters is theoretically 100%. However, losses occur due to path resistance and parasitic capacitance. While the buck, boost, and buck-boost converters have high efficiency, they may exhibit low speed.
FIG. 4A is a schematic of a linear amplifier (LA) 400. An LA is an electronic circuit whose output is proportional to its input (e.g. Vout may be much less than Vin), and is capable of delivering more power into a load. There are different classes of LA (e.g., class A, class B, class AB, etc.). A class A LA can exhibit good linearity in both single ended and push-pull topologies. Class B and class AB LAs can exhibit linearity only in the push-pull topology, in which two active elements (e.g. transistors) are used to amplify positive and negative parts of a radio frequency (RF) cycle respectively.
Referring to FIG. 4A, the LA 400 includes a first PMOS transistor P1, a first NMOS transistor N1, and a load represented by a resistor 401.
FIG. 4B is a graph of Vout versus Vin for the LA 400.
The efficiency of an LA is theoretically 0% to approximately 78.5% (π/4) due to voltage drops of the technology (e.g. complementary MOS (CMOS)) in which the LA 400 is implemented. While the LA 400 has low efficiency, it can exhibit high speed.